C8051T610DB24【PDF 171/218 页】DAUGHTER BOARD T610 24QFN SOCKET

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C8051T610/1/2/3/4/5/6/7

SFR Definition 25.1. CKCON: Clock Control

Bit

Name

Type

Reset

7

T3MH

R/W

0

6

T3ML

R/W

0

5

T2MH

R/W

0

4

T2ML

R/W

0

3

T1M

R/W

0

2

T0M

R/W

0

1

0

SCA[1:0]

R/W

0

0

SFR Address = 0x8E

Bit Name

Function

7

6

5

4

3

2

T3MH

T3ML

T2MH

T2ML

T1

T0

Timer 3 High Byte Clock Select.

Selects the clock supplied to the Timer 3 high byte (split 8-bit timer mode only).

0: Timer 3 high byte uses the clock defined by the T3XCLK bit in TMR3CN.

1: Timer 3 high byte uses the system clock.

Timer 3 Low Byte Clock Select.

Selects the clock supplied to Timer 3. Selects the clock supplied to the lower 8-bit timer

in split 8-bit timer mode.

0: Timer 3 low byte uses the clock defined by the T3XCLK bit in TMR3CN.

1: Timer 3 low byte uses the system clock.

Timer 2 High Byte Clock Select.

Selects the clock supplied to the Timer 2 high byte (split 8-bit timer mode only).

0: Timer 2 high byte uses the clock defined by the T2XCLK bit in TMR2CN.

1: Timer 2 high byte uses the system clock.

Timer 2 Low Byte Clock Select.

Selects the clock supplied to Timer 2. If Timer 2 is configured in split 8-bit timer mode,

this bit selects the clock supplied to the lower 8-bit timer.

0: Timer 2 low byte uses the clock defined by the T2XCLK bit in TMR2CN.

1: Timer 2 low byte uses the system clock.

Timer 1 Clock Select.

Selects the clock source supplied to Timer 1. Ignored when C/T1 is set to 1.

0: Timer 1 uses the clock defined by the prescale bits SCA[1:0].

1: Timer 1 uses the system clock.

Timer 0 Clock Select.

Selects the clock source supplied to Timer 0. Ignored when C/T0 is set to 1.

0: Counter/Timer 0 uses the clock defined by the prescale bits SCA[1:0].

1: Counter/Timer 0 uses the system clock.

1:0

SCA[1:0] Timer 0/1 Prescale Bits.

These bits control the Timer 0/1 Clock Prescaler:

00: System clock divided by 12

01: System clock divided by 4

10: System clock divided by 48

11: External clock divided by 8 (synchronized with the system clock)

Rev 1.1

171

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